The NAND type flash memory cells may have a problem in that with the progress of fine patterning, their coupling ratio would lower and so operation voltage is increased. To solve this problem, such a NAND type flash memory cell is proposed as to have a floating gate that includes a plurality of first conductive films and a plurality of second conductive films stacked alternately on each other and has an irregular-shaped side wall and a control gate electrode that is disposed on the top surface and the irregular-shaped side wall of this floating gate (see, for example, Japanese Patent Application Laid-Open No. 2004-207695). Such a structure increases an area in which the floating gate and the control gate electrode overlap and so increases an electrostatic capacitance between them, thereby enabling increasing of the coupling ratio.
With the progress of fine patterning, the size of the cell becomes about twice the thickness of an insulating film between the control gate electrode and the floating gate, so that it is difficult to form the control gate electrode on the side wall of the floating gate.